This application claims the priority benefit of Taiwan application serial no. 89111584, filed Jun. 14, 2000.
1. Field of Invention
The present invention relates to a capacitance measurement circuit. More particularly, the present invention relates to a measurement circuit for measuring the capacitance of a metallic parasitic capacitor on a silicon chip.
2. Description of Related Art
In semiconductor fabrication, metallic interconnects are often used to link up various devices. Due to the coupling between a metallic interconnect and a substrate or between pairs of metallic interconnects, metallic parasitic capacitance are formed. Since the response of a transistor is often delayed by the presence of metallic parasitic capacitance, the magnitude of the parasitic capacitance is preferably measured in advance so that its overall effect on chip performance can be accessed.
Parasitic capacitance can be directly measured by a high-precision capacitor meter. However, direct measurement of capacitance by a capacitor meter is feasible only for the measurement of capacitance in the pico-farad (PF) range (that is, 10xe2x88x9212 Farad). Due to rapid progress in semiconductor manufacturing technologies, the width of metallic interconnects continues to shrink to a smaller dimension. Hence, magnitude of the metallic parasitic capacitance in a silicon chip correspondingly decreases to the femto-farad (FF) range (that is, 10xe2x88x9215 Farad). For such a small capacitance, the value of parasitic capacitance can no longer be accurately measured by a capacitor meter.
The conventional method of measuring a low capacitance value includes the use of a charge-based capacitance measurement (CBCM) circuit. FIG. 1 is a schematic circuit diagram of a conventional CBCM circuit. The capacitance measurement circuit actually comprises of two pairs of symmetrical and matching MOS transistor circuits. One transistor circuit includes a pair of PMOS transistors 106 and 110 while the other transistor circuit includes a pair of NMOS transistors 108 and 112.
As shown in FIG. 1, a current meter 102 is serially connected between a power supply 100 and PMOS transistor 106 on the left side of the capacitance measurement circuit. Current meter 102 measures the current flowing from power source 100 to the source terminal of PMOS transistor 106. Another current meter 104 on the right side of the capacitance measurement circuit is serially connected to power source 100 and PMOS transistor 110. Similarly, current meter 104 measures the current flowing from power source 100 to the source terminal of PMOS transistor 110.
On the left side, the drain terminal of PMOS transistor 106 and the drain terminal of NMOS transistor 108 are connected in parallel with a m1 metal strip 114. Assume that the parasitic capacitor formed between metal strip 114 and the substrate has a capacitance Cwire. Similarly on the right side, the drain terminal of PMOS transistor 110 and the drain terminal of NMOS transistor 112 are connected in parallel with a m1 metal strip 116. Assume the parasitic capacitor that is formed from m1 metal strip 116 and a m2 metal strip 118 has a capacitance of Cx and the parasitic capacitor that forms from m1 metal strip 116 and the substrate has a capacitance Cwire. Metal strip 118 is connected to the ground. In addition, m1 metal strip 114 and m1 metal strip 116 are symmetrical to each other. With such a configuration, the metallic parasitic capacitance measured via the drain terminal of PMOS transistor 110 should be Cwire +Cx.
The gate terminal of PMOS transistor 106 and the gate terminal of PMOS transistor 110 are connected in parallel to the output terminal V1 of a signal generator 120. The gate terminal of NMOS transistor 108 and the gate terminal of NMOS transistor 112 are connected in parallel to another output terminal V2 of signal generator 120. The source terminal of NMOS transistor 108 and the source terminal of NMOS transistor 112 are connected in parallel to the ground.
FIG. 2 is a timing diagram showing the signals needed for a conventional CBCM circuit during operation. As shown in FIG. 2, control signals needed for the CBCM circuit are generated by signal generator 120. Signal generator 120 issues control signals V1 to the gate terminal of PMOS transistor 106 and the gate terminal of PMOS transistor 110. Signal generator 120 also issues control signals V2 to the gate terminal of NMOS transistor 108 and the gate terminal of NMOS transistor 112. Ideally, a conventional CBCM circuit should operate in steps according to the timing diagram in FIG. 2. The steps includes:
Step one: During time interval t0-t1, all MOS transistors are in the shut-off state, and both current meters 102 and 104 register a zero current;
Step two: During time interval time t1-t2, PMOS transistor 106 and PMOS transistor 110 are in a conductive state while NMOS transistor 108 and NMOS transistor 112 are in a shut-off state. During this period, capacitor Cwire (that is, m1 metal strip 114) and capacitor Cwire+Cx (that is, m1 metal strip 116 and m2 metal strip 118) are charged. Consequently, currents of different values pass through the respective current meters 102 and 104;
Step three: During time interval t2-t3, all MOS transistors are in the shut-off state, and both current meters 102 and 104 register a zero current;
Step four: During time interval t3-t4, both PMOS transistors 106 and 110 are in a shut-off state while both NMOS transistors 108 and 112 are in a conductive state. During this period, capacitor Cwire (that is, m1 metal strip 114) and capacitor Cwire+Cx (that is, m1 metal strip 116 and m2 metal strip 118) are discharged.
In the aforementioned four steps, the average current flowing through current meter 102 is Iwire and the average current flowing through current meter 104 is Iwire+x.
The value of capacitance Cx can be deduced using the following formulae:
Iwire+x=(Cwire+Cx)xc2x7Vddxc2x7f;
Iwire=Cwirexc2x7Vddxc2x7f;
            C      x        =                            I                      wire            +            x                          -                  I          wire                            Vdd        ·        f              ,
where f is the frequency (as shown in FIG. 2).
In practice, at time t2, PMOS transistor 106 and PMOS transistor 110 begin to change from a conductive state to a shut-off state while NMOS transistor 108 and NMOS transistor 112 are in a shut-off state. An equivalent capacitance between the source terminal and the gate terminal of PMOS transistor 106 can be obtained by looking up the gate terminal of PMOS transistor 106. Similarly, an equivalent capacitance between the source terminal and the gate terminal of PMOS transistor 106 and the capacitor Cwire can be obtained by looking down the gate terminal of PMOS transistor 106. Similarly, an equivalent capacitance between the source terminal and the gate terminal of PMOS transistor 110 can be obtained by looking up the gate terminal of PMOS transistor 110. An equivalent capacitance between the source terminal and the gate terminal of PMOS transistor 110 and the capacitor Cwire+Cx can be obtained by looking down the gate terminal of PMOS transistor 110.
FIG. 3 is a graph showing the time trace of negative current produced by a conventional CBCM circuit through a SPICE simulation. At time t2 (control signal V1304 changes from a ground voltage to a voltage Vdd as shown in FIG. 3), a negative current iwire returns from the gate terminal of PMOS transistor 106 to current meter 102 and a negative current Iwire+x returns from the gate terminal of PMOS 110 to current meter 103. As shown in FIG. 3, negative current iwire 302 differs from negative current Iwire+x 300 because capacitance looking into the lower portion from the gate terminal of PMOS transistor 110 is greater than the capacitance looking into the lower portion from the gate terminal of PMOS transistor 106 by Cx. The difference between negative current iwire 302 and negative current iwire+x 300 often leads to an error in the measurement of capacitance Cx.
Accordingly, one object of the present invention is to provide a capacitance measurement circuit capable of limiting measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors to current measurement devices so that accuracy of capacitance measurement is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip capacitance measurement circuit. The measurement circuit includes a plurality of MOS transistors formed into a pair of symmetrical circuits. The chip capacitance measurement circuit utilizes the difference in average current flowing to the respective left capacitance and right capacitance of the measurement circuit. A power supply provides power to the measurement circuit. A current measuring device is installed between the power supply and the measurement circuit for measuring the value of the current flowing from the power source to the measuring circuit. A signal generator is coupled to the measurement circuit for providing a set of control signals to the measurement circuit.
The signal generator provides control signals to the measurement circuit such that the MOS transistors within the measurement circuit are conductive or shut in sequential order. Since the negative current that returns to the current measuring device originally generated by the respective symmetrical components of the measurement circuit are identical, capacitance of the chip capacitor can be accurately measured.
This invention also provides a capacitance measurement circuit for measuring chip capacitance. The capacitance measurement circuit includes a measurement circuit, a power supply, a first current meter, a second current meter and a signal generator. The first current meter and the second current meter are devices coupled between the power supply and the measurement circuit. The first and second current meters are used for measuring the values of current flowing from the power supply to the respective symmetrical component circuits of the measurement circuit. The signal generator is coupled to the measurement circuit for providing a set of control signals to the measurement circuit. The measurement circuit includes a first pair of completely matched MOS transistors, a second pair of completely matched MOS transistors and a third pair of completely matched MOS transistors. The first pair of MOS transistors comprises of a first PMOS transistor and a second PMOS transistor. The source terminal of the first PMOS transistor is connected to the first current meter. The source terminal of the second PMOS transistor is connected to the second current meter. The gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor are connected in parallel to the first output terminal of the signal generator. The second pair of MOS transistors comprises of a third PMOS transistor and a fourth PMOS transistor. The source terminal of the third PMOS transistor is connected to the drain terminal of the first PMOS transistor. The source terminal of the fourth PMOS transistor is connected to the drain terminal of the second PMOS transistor. The gate terminal of the third PMOS transistor and the gate terminal of the fourth PMOS transistor are connected in parallel to the second output terminal of the signal generator. The third pair of MOS transistors comprises of a first NMOS transistor and a second NMOS transistor. The drain terminal of the first NMOS transistor is connected to the drain terminal of the third PMOS transistor and one terminal of the left wire capacitor while the other terminal of the left wire capacitor is connected to ground. The drain terminal of the second NMOS transistor is connected to the drain terminal of the fourth PMOS transistor, one terminal of the right wire capacitor and one terminal of a to-be-measured capacitor, while the other terminal of the right wire capacitor and the other terminal of the to-be-measured capacitor are both connected to the ground. The gate terminal of the first NMOS transistor and the gate terminal of the second NMOS transistor are connected in parallel to the third output terminal of the signal generator. The source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor are connected in parallel to the ground.
The signal generator provides control signals to the measurement circuit so that the first pair of PMOS transistors, the second pair of PMOS transistors and the third pair of NMOS transistors are conductive or shut in sequential order. Since the negative current that returns to the first current meter and the second current meter originally generated by the respective symmetrical components of the measurement circuit are identical, capacitance of the chip capacitor can be accurately measured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.